7641 datasheet(159/385 Pages) RENESAS

159 / 385 page

Rev.2.00

Aug 28, 2006

page 28 of 148

7641 Group

REJ09B0336-0200

APPLICATION

2.2 Timer

Fig. 2.2.20 Related registers setting

ICONB

T14A16

0916

CPMA

T123M

CPU mode register A (address 0016)

Processor mode bits

Stack page select bit

Main clock (XIN-XOUT): Oscillating

Internal system clock: f(XIN)

Set an initial value.

Interrupt control register B (address 0616)

Timer 123 mode register (address 2916)

Timer 1 count: Stopped (Set to “0” after initialization.)

Timer 1 count source:

φ / 8

Timer 2 count source: Timer 1’s underflow

Timers 1, 2 write control: Written at the same time

Timer 1 (address 2416)

Timer 2 (address 2516)

Timer X interrupt: Disabled

Timer 1 interrupt: Disabled

Timer 2 interrupt: Enabled

TYL

FF16

TYH

FF16

TYM

Set “division ratio – 1” = 74 (4A16)

Timer Y mode register (address 2816)

Timer Y write control: Written at the same time

TYOUT output: Disabled

Event counter mode

Count at rising edge of CNTR1

Timer Y count: Stopped (Set to “0” after initialization.)

Timer YL (low) (address 2216)

Timer YH (high) (address 2316)

CCR

Clock control register (address 1F16)

System clock: f(XIN)/2

00 00

P4D

Port P4 direction register (address 1916)

Set to input mode.

Set “division ratio – 1” = 9 (0916)

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