7641 datasheet(156/385 Pages) RENESAS

156 / 385 page

Rev.2.00

Aug 28, 2006

page 25 of 148

7641 Group

REJ09B0336-0200

APPLICATION

2.2 Timer

Fig. 2.2.17 Relevant registers setting

ICONB

TXL

3F16

TXH

0016

TXM

00 0

CPMA

CPU mode register A (address 0016)

Processor mode bits

Stack page select bit

Main clock (XIN-XOUT): Oscillating

Internal system clock: f(XIN)

Set “division ratio – 1” = 63 (3F16)

Interrupt control register B (address 0616)

Timer X mode register (address 2716)

Timer X write control: Written at the same time

Timer X count source:

φ / 8

Timer X internal clock:

φ / n

Pulse output mode

Pulse output: Start from “H” output

Timer X count: Stopped

Timer XL (low) (address 2016)

Timer XH (high) (address 2116)

Timer X interrupt: Disabled

CCR

Clock control register (address 1F16)

System clock: f(XIN)

0 000

0116

Port P4 (address 1816)

Set an initial value.

P4D

Port P4 direction register (address 1916)

Set to output mode.

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