7641 datasheet(206/385 Pages) RENESAS

206 / 385 page

Rev.2.00

Aug 28, 2006

page 75 of 148

7641 Group

REJ09B0336-0200

APPLICATION

2.4 UART

Fig. 2.4.22 Control procedure (1)

P3 (Address : 0E16), bit1?

U1CON (Address : 3316)

010x10002

010x10102

• Countermeasure for a bit slippage

U1CON (Address : 3316), bit1

• Reception starts.

RESET

Initialization

q x: This bit is not used here. Set it to “0” or “1” arbitrarily.

CLI

•

φ as UART clock, Clock prescaling 1/1, 1 stop bit,

Parity checking disabled, 8-bit character length

• Port P31 to input mode

• UART1 receive interrupt enabled

• UART1 summing error interrupt enabled

(Address : 3116)

(Address : 3316), bit2

(Address : 3316), bit4

(Address : 3016)

(Address : 3316), bit5

(Address : 0F16), bit1

(Address : 0516), bit6

(Address : 0616), bit0

U1BRG

U1CON

U1MOD

U1CON

P3D

ICONA

ICONB

1916

010x00002

Main process

RTI

Note 1: When using Index X mode flag (T)

Note 2: When using Decimal mode flag (D)

•Push registers used in interrupt process routine

Pop registers

CLT (Note 1)

CLD (Note 2)

Push registers to stack

UART1 summing error interrupt routine

Error process

7641 Datasheet(PDF) 206 Page - Renesas Technology Corp

7641 Datasheet(HTML) 206 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL