7641 datasheet(215/385 Pages) RENESAS

215 / 385 page

Rev.2.00

Aug 28, 2006

page 84 of 148

7641 Group

REJ09B0336-0200

APPLICATION

2.5 DMAC

Fig. 2.5.5 Structure of DMAC channel 1 mode register 2

DMAC channel 1 mode register 2

b7 b6 b5 b4 b3 b2 b1 b0

DMAC channel 1 mode register 2

(DMA1M2 : address 4116) (Note 1)

Name

Functions

At reset R W

b3b2b1b0

0 0 0 0 : Not used

0 0 0 1 : UART2 receive interrupt

0 0 1 0 : UART2 transmit interrupt

0 0 1 1 : Timer X interrupt

0 1 0 0 : INT1 interrupt

0 1 0 1 : USB endpoint 1 IN_PKT_RDY

signal (falling edge active)

0 1 1 0 : USB endpoint 2 IN_PKT_RDY

signal (falling edge active)

0 1 1 1 : USB endpoint 4 IN_PKT_RDY

signal (falling edge active)

1 0 0 0 : USB endpoint 1

OUT_PKT_RDY signal (rising

edge active)

1 0 0 1 : USB endpoint 1

OUT_FIFO_NOT_EMPTY

signal (rising edge active)

1 0 1 0 : USB endpoint 2

OUT_PKT_RDY signal

(rising edge active)

1 0 1 1 : USB endpoint 4

OUT_PKT_RDY signal

(rising edge active)

1 1 0 0 : Master CPU bus interface

OBE1 signal (rising edge active)

1 1 0 1 : Master CPU bus interface IBF1

signal, data (rising edge active)

1 1 1 0 : Timer 1 interrupt

1 1 1 1 : CNTR0 interrupt

0 : No action

1 : Request of channel 1 transfer by

writing “1”

DMAC channel 1 hardware

transfer request source

bits (D1HR)

DMAC channel 1 software

transfer trigger (D1SWT)

0 : Disabled

1 : Enabled

0 : No action

1 : Reset of channel 1 capture register by

writing “1”

DMAC channel 1 USB and

master CPU bus interface

enable bit (D1UMIE)

DMAC channel 1 transfer

initiation source capture

DMAC channel 1 enable

bit (D1CEN)

0 : Channel 1 disabled

1 : Channel 1 enabled (Note 3)

(Note 2)

Notes 1: DMAC channel 0 mode register 2 and DMAC channel 1 mode register 2 are

assigned at the same address 4116. The accessible register depends on channel

index bit, bit 7 of DMAC index and status register.

2: These bits’ contents are “0” at read. This bit is automatically cleared to “0” after

writing “1”.

3: When setting this bit to “1”, simultaneously set the DMAC channel 1 transfer

initiation source capture register reset bit (bit 6 of DMA1M2) to “1”.

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