7641 datasheet(213/385 Pages) RENESAS

213 / 385 page

Rev.2.00

Aug 28, 2006

page 82 of 148

7641 Group

REJ09B0336-0200

APPLICATION

2.5 DMAC

(3) DMAC channel x (x = 0, 1) mode register 2

•DMAC channel x software transfer trigger bit (DxSWT)

Writing “1” to the DxSWT bit can generate a transfer request as a software trigger. If all of DMACx

hardware transfer request source bits (DxHR) are “0”, the software trigger is only transfer request

factor. This bit is fixed to “0” at read.

•DMAC channel x USB and master CPU bus interface enable bit (DxUMIE)

When both USB and master CPU bus interface is used as a hardware transfer request source, set

the DxUMIE bit to “1”. When not that the master CPU bus interface is used, but that the USB is

only used, set the DxUMIE bit to “0” (disabled).

•DMAC channel x transfer initiation source capture register reset bit (DxCRR)

Writing “1” to the DxCRR bit can reset the transfer initiation source capture register. The request

of the transfer initiation source is latched asynchronously and it is sampled into the transfer

initiation source capture register at a rising edge of

φ. This bit is fixed to “0” at read.

•DMAC channel x enable bit (DxCEN)

The DMAC channel x is enabled by setting this bit to “1”. When clearing this to “0”, the DMA

transfer is finished.

7641 Datasheet(PDF) 213 Page - Renesas Technology Corp