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7641 Datasheet(PDF) 235 Page - Renesas Technology Corp |
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7641 Datasheet(HTML) 235 Page - Renesas Technology Corp |
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235 / 385 page ![]() Rev.2.00 Aug 28, 2006 page 104 of 148 7641 Group REJ09B0336-0200 APPLICATION 2.7 Frequency synthesizer (PLL) Fig. 2.7.6 Structure of Frequency synthesizer divide register Frequency synthesizer divide register b7 b6 b5 b4 b3 b2 b1 b0 Frequency synthesizer divide register (FSD: address 6F16) b 0 1 Functions At reset R W 1 1 2 1 3 1 4 1 5 1 6 1 7 1 qfSYN clock is generated by dividing fVCO clock by the contents of this register: fSYN = fVCO / {2(m +1)}, m: value set to FSD |
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