7641 datasheet(238/385 Pages) RENESAS

238 / 385 page

Rev.2.00

Aug 28, 2006

page 107 of 148

7641 Group

REJ09B0336-0200

APPLICATION

2.7 Frequency synthesizer (PLL)

(4) Recovering from hardware reset

The frequency synthesizer and DC-DC converter must be set up as follows when recovering from

a Hardware Reset:

x Enable the frequency synthesizer after setting the frequency synthesizer related registers (addresses

6C16 to 6F16). Then wait for 2 ms.

y Check the frequency synthesizer lock status bit. If “0”, wait for 0.1 ms and then recheck.

z To use the intermediate current, set the LPF current control bits of frequency synthesizer control

{ When using the USB built-in DC-DC converter, set the USB line driver supply enable bit of the

USB control register (address 1316) to “1”. This setting must be done 2 ms or more later than

the setup described in step x. The USB line driver current control bit must be set to “0” at this

time. (When Vcc = 3.3V, the setting explained in this step is not necessary.)

| After waiting for (C + 1) ms so that the external capacitance pin (Ext. Cap. pin) can reach

approximately 3.3 V, set the USB clock enable bit to “1”. At this time, “C” equals the capacitance

(

µF) of the capacitor connected to the Ext. Cap. pin. For example, if 2.2 µF and 0.1 µF

capacitors are connected to the Ext. Cap. in parallel, the required wait will be (2.3 + 1) ms.

} After enabling the USB clock, wait for 4 or more

φ cycles, and then set the USB enable bit to

“1”.

Do not write to any of the USB internal registers (addresses 5016 to 6416) until the USB clock

enabled, except for the USB control register (address 1316), clock control register (address

1F16), and frequency synthesizer control register (address 6C16).

2.7.4 Notes on frequency synthesizer

•Bits 6 and 5 of the frequency synthesizer control register (address 6C16) are initialized to (b6, b5) = “11”

after reset release. Make sure to set bits 6 and 5 to “10” after the frequency synthesizer lock status

bit goes to “1”.

•Use the frequency synthesizer output clocks 2 ms to 5 ms later than setting the frequency synthesizer

enable bit to “1” (enabled). After that do not change any register values because it might cause output

clocks unstabilized temporarily.

•Make sure to connect a low-pulse filter to the LPF pin when using the frequency synthesizer.

•The frequency synthesizer divide register set value never affects fUSB frequency.

•When using the fSYN as an internal system clock, set the frequency synthesizer divide register so that

fSYN could be 24 MHz or less.

•When using the frequency synthesized clock function, we recommend using the fastest frequency

possible of f(XIN) or f(XCIN) as an input clock for the PLL.

•Set the value of frequency synthesizer multiply register 2 (FSM2) so that the fPIN is 1 MHZ or higher.

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