7641 datasheet(240/385 Pages) RENESAS

240 / 385 page

Rev.2.00

Aug 28, 2006

page 109 of 148

7641 Group

REJ09B0336-0200

APPLICATION

2.8 Master CPU bus interface

2.8.2 Related registers

Fig. 2.8.2 Structure of Data bus buffer register x (x = 0, 1)

Data bus buffer register x

b7 b6 b5 b4 b3 b2 b1 b0

Data bus buffer register x (x = 0, 1)

(DBBx: addresses 4816, 4C16)

Functions

At reset R W

qA data is latched into this register by a write request from the host

CPU.

qWrite an output data into this register.

The data is output on to the data bus by a read request from the

host CPU.

Data bus buffer status register x

b7 b6 b5 b4 b3 b2 b1 b0

Data bus buffer status register x (x = 0, 1)

(DBBSx: addresses 4916, 4D16)

Name

Functions

At reset R W

Input buffer full flag (IBFx)

A0 flag (A0x)

User definable flag

(U4 to U7)

User definable flag (U2)

0 : Buffer empty

1 : Buffer full

0 : Buffer empty

1 : Buffer full

This flag can be defined by user freely.

Output buffer full flag

(OBFx)

This flag indicates the condition of A0

status when the IBFx flag is set.

This flag can be defined by user freely.

Fig. 2.8.3 Structure of Data bus buffer status register x (x = 0, 1)

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