7641 datasheet(243/385 Pages) RENESAS

243 / 385 page

Rev.2.00

Aug 28, 2006

page 112 of 148

7641 Group

REJ09B0336-0200

APPLICATION

2.8 Master CPU bus interface

Fig. 2.8.6 Connection example

Host CPU

7641 group

Host CPU

7641 group

D0 to D7

DQ0 to DQ7

R,W separate type bus

D0 to D7

DQ0 to DQ7

R/W type bus

R/W

ASx

(1) Data bus buffer mode

The selection of either the single data bus buffer mode or the double data bus buffer mode can be

performed by the Data Bus Buffer Function Select Bit.

•Single data bus buffer mode

The data bus buffer 0 of 1 byte only is used.

•Double data bus buffer mode

The data bus buffer 0 and data bus buffer 1, totalling 2 bytes, are used.

(2) Interrupt

•Input buffer full interrupt

When the data is input to the data bus buffer register x, the Input Buffer Full Flag (IBFx ; x = 0,

1) is set to “1” and the interrupt request occurs. When the data is read out from the data bus buffer

•Output buffer empty interrupt

When the data is written to the data bus buffer register x, the Output Buffer Full Flag (OBFx ; x

= 0, 1) is set to “1”. When the host CPU reads out from the data bus buffer register x, the OBFx

flag is cleared to “0” and the output buffer empty interrupt request occurs.

7641 Datasheet(PDF) 243 Page - Renesas Technology Corp