7641 datasheet(246/385 Pages) RENESAS

246 / 385 page

Rev.2.00

Aug 28, 2006

page 115 of 148

7641 Group

REJ09B0336-0200

APPLICATION

2.8 Master CPU bus interface

Fig. 2.8.8 Control procedure

2.8.6 Notes on master CPU bus interface

Be sure to set port P6 to input mode by setting the port P6 direction register to “0” when the master CPU

bus interface is enabled.

DBBC0 (address 4A16)

DBBC1 (address 4E16)

ICONC(address 0716)

DBBC0 (address 4A16),bit6

CLI

000000112

00011X002

XX11XXXX2

DBBS0 (address 4916),bit3 ?

RESET

•OBF0, IBF0

output enabled

•Output buffer 0 empty interrupt enabled

•Input buffer 0 full interrupt enabled

•Single data bus buffer mode

•Master CPU bus interface enabled

Input buffer 0 full interrupt

Read Data bus buffer

(command)

RTI

Initialization

q x: This bit is not used here. Set it to “0” or “1” arbitrarily.

CLT (Note 1)

CLD (Note 2)

Push registers to stack

Read Data bus buffer

(data)

Pop registers

Write data into Data bus buffer register 0

CLT (Note 1)

CLD (Note 2)

Push registers to stack

Output buffer 0 empty interrupt

Note1: When using Index X mode flag (T)

2: When using Decimal mode flag (D)

•Push registers used in interrupt process routine

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