7641 datasheet(245/385 Pages) RENESAS

245 / 385 page

Rev.2.00

Aug 28, 2006

page 114 of 148

7641 Group

REJ09B0336-0200

APPLICATION

2.8 Master CPU bus interface

Fig. 2.8.7 Setting of relevant registers

2.8.5 Master CPU bus interface application example

(1) Data communication with host CPU

Outline : The MCU communicates with the host CPU by using the single data bus buffer mode.

Figure 2.8.7 shows a setting of the related registers and Figure 2.8.8 shows a control procedure.

OBF0 output enabled

Data bus buffer control register 0 (address 4A16)

DBBC0

IBF0 output enabled

IBF0 interrupt occurrence due to write of data or command

Output buffer 0 empty interrupt enabled

Input buffer 0 full interrupt enabled

Data bus buffer register 0 (address 4816)

DBB0

0 0 0

DBBC1

ICONC

Data read/write

Data bus buffer status register 0 (address 4916)

DBBS0

Master CPU bus interface disabled

(After initialization setting, set this to “1”.)

RD, WR separate type bus

Data bus buffer control register 1 (address 4E16)

P74 functions as I/O port.

P73 functions as I/O port.

Output buffer 1 empty interrupt disabled

Input buffer 1 full interrupt disabled

Single data bus buffer mode

Interrupt control register C (address 0716)

Input buffer full interrupt enabled

Output buffer empty interrupt enabled

Output buffer full flag

Input buffer full flag

A0 flag

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