7641 datasheet(242/385 Pages) RENESAS

242 / 385 page

Rev.2.00

Aug 28, 2006

page 111 of 148

7641 Group

REJ09B0336-0200

APPLICATION

2.8 Master CPU bus interface

2.8.3 Functional description

The internal 2-byte bus interface can be controlled by the signals from the host CPU side; it is called the

slave mode. This bus interface allows the 7641 group to be directly connected with a R/W type of CPU

bus or a RD and WR separate type of CPU bus.

Ports P52 to P57, P60 to P67, P72 to P74 become the master CPU bus interface function pins when the

master CPU bus interface is enabled.

P60 to P67: Function as data I/O pins (DQ0 to DQ7). (Be sure to set them to input mode by setting the port

P6 direction register to “0”.)

P52, P74: Function as the status signal OBFx (x = 0, 1). The state of the output buffer DBBx (x = 0, 1) is

output.

P53, P73: Function as the status signal IBFx (x = 0, 1). The state of the input buffer DBBx (x = 0, 1) is

output.

P54, P72: Function as the status signal Sx (x = 0, 1). The chip select signals from the host CPU are input.

P55: Functions as the status signal A0. When A0 is “H”, the host CPU can read the contents of the data

bus buffer status register x (x = 0, 1) (addresses 4916, 4D16). When A0 is “L”, the contents of data bus

buffer register x (x = 0, 1) can be output owing to a read request from the host CPU.

When a data is written into the data bus buffer register x (x = 0, 1), if A0 is “L”, this indicates that its

contents are the data; if “H”, this indicates that they are the command.

P72 to P74 become the master CPU bus interface function pins only when the double data bus buffer mode

is used.

Tables 2.8.1 and 2.8.2 shows the bus control signal and data bus state; Figure 2.8.6 shows a connection

example.

Sx signal

RD signal

–

WR signal

–

A0 signal

–

Data bus state

Read

Write

High-impedance

Data on data bus

Output data

DBBSx contents

Input data (data)

Input data (command)

–

Table 2.8.1 Bus control signal and data bus state-RD/WR separate type

Sx signal

R/W signal

–

E signal

–

A0 signal

–

Data bus state

Read

Write

High-impedance

Data on data bus

Output data

DBBSx contents

Input data (data)

Input data (command)

–

Table 2.8.2 Bus control signal and data bus state-R/W type

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