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7641 Datasheet(PDF) 239 Page - Renesas Technology Corp |
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7641 Datasheet(HTML) 239 Page - Renesas Technology Corp |
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239 / 385 page ![]() Rev.2.00 Aug 28, 2006 page 108 of 148 7641 Group REJ09B0336-0200 APPLICATION 2.8 Master CPU bus interface 2.8 Master CPU bus interface This paragraph explains the registers setting method and the notes related to the master CPU bus interface. 2.8.1 Memory map Fig. 2.8.1 Memory map of registers related to master CPU bus interface 004D16 Data bus buffer register 1 (DBB1) 004C16 004A16 Data bus buffer status register 0 (DBBS0) Data bus buffer register 0 (DBB0) Interrupt control register C (ICONC) 004916 004816 000716 Interrupt request register C (IREQC) 000416 Address Data bus buffer control register 0 (DBBC0) Data bus buffer status register 1 (DBBS1) Data bus buffer control register 1 (DBBC1) 004E16 |
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