7641 datasheet(270/385 Pages) RENESAS

270 / 385 page

Rev.2.00

Aug 28, 2006

page 139 of 148

7641 Group

REJ09B0336-0200

APPLICATION

2.12 Clock generating circuit

Item

Oscillation

CPU

Internal clock

I/O ports

Timer

UART

DMAC

Serial I/O

USB

RAM

SFR

CPU registers

State in Stop mode

Stopped.

Stopped at “H” level.

Retains the state at the STP instruction execution.

When using internal count source: Stopped.

When using external count source: Operating.

Stopped.

When using internal syncronous clock: Stopped.

When using external syncronous clock: Operating.

Stopped.

Retained.

Retained (except for Timer 1, Timer 2).

Retained: Accumulator, Index register X, Index register Y, Stack

pointer, Program counter, Processor status register.

2.12.3 Stop mode

The Stop mode is set by executing the STP instruction. In Stop mode, the oscillation of both clocks (XIN–

XOUT, XCIN–XCOUT) stop and the internal clock

φ stops at the “H” level. The CPU stops and peripheral units

stop operating. As a result, power dissipation is reduced.

(1) State in Stop mode

Table 2.12.1 shows the state in Stop mode.

Table 2.12.1 State in Stop mode

(2) Release of Stop mode

The Stop mode is released by a reset input or by the occurrence of an interrupt request.

These interrupt sources can be used for restoration:

•INT0, INT1

•CNTR0, CNTR1

•Timers X, Y using an external count source

•Serial I/Os using an external clock

•Key-on wake-up

•USB function resume

However, when using any of these interrupt requests for restoration from Stop mode, in order to

enable the selected interrupt, set the following conditions before execution of STP instruction.

[Necessary register setting]

➀ Timer 1 interrupt enable bit (b6 of ICONB) = “0” (interrupt disabled)

➁ Timer 2 interrupt enable bit (b7 of ICONB) = “0” (interrupt disabled)

➂ Timer 1 interrupt request bit (b6 of IREQB) = “0” (no interrupt request issued)

➃ Timer 2 interrupt request bit (b7 of IREQB) = “0” (no interrupt request issued)

➄ Interrupt request bit of interrupt source to be used for restoration = “0” (no interrupt request issued)

➅ Interrupt enable bit of interrupt source to be used for restoration = “1” (interrupts enabled)

➆ Interrupt disable flag I = “0” (interrupt enabled)

(3) Notes on STP instruction

•Execution of STP instruction clears the timer 123 mode register (address 2916) except bit 4 to “0”.

•When using fSYN as the internal system clock, switch to f(XIN) or f(XCIN) before execution of STP instruction.

•Execution of STP instruction clears bit 7 of clock control register to “0” (f(XIN)/2).

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