7641 datasheet(271/385 Pages) RENESAS

271 / 385 page

Rev.2.00

Aug 28, 2006

page 140 of 148

7641 Group

REJ09B0336-0200

APPLICATION

2.12 Clock generating circuit

2.12.4 Wait mode

The Wait mode is set by execution of the WIT instruction. In Wait mode, oscillation continues, but the

internal clock

φ stops at the “H” level.

The CPU stops, but most of the peripheral units continue operating.

(1) State in Wait mode

Table 2.12.2 shows the state in Wait mode.

Table 2.12.2 State in Wait mode

Item

Oscillation

CPU

Internal clock

I/O ports

Timer

UART

DMAC

Serial I/O

USB

RAM

SFR

CPU registers

State in Wait mode

Oparating.

Stopped.

Stopped at “H” level.

Retains the state at the WIT instruction execution.

Operating.

Stopped.

Operating.

Retained.

Retained: Accumulator, Index register X, Index register Y, Stack

pointer, Program counter, Processor status register.

(2)

Release of wait mode

The Wait mode is released by reset input or by the occurrence of an interrupt request.

In Wait mode oscillation is continued, so that an instruction can be executed immediately after the

Wait mode is released.

These interrupt sources can be used for restoration:

•INT0, INT1

•CNTR0, CNTR1

•Timers

•Serial I/Os

•UART

•DMAC

•Key-on wake-up

•Master CPU bus interface

•USB function

•USB SOF

However, when using any of these interrupt requests for restoration from Stop mode, in order to

enable the selected interrupt, set the following conditions before execution of WIT instruction.

[Necessary register setting]

➀ Interrupt request bit of interrupt source to be used for restoration = “0” (no interrupt request issued)

➁ Interrupt enable bit of interrupt source to be used for restoration = “1” (interrupts enabled)

➂ Interrupt disable flag I = “0” (interrupt enabled)

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