7641 datasheet(308/385 Pages) RENESAS

308 / 385 page

Rev.2.00

Aug 28, 2006

page 29 of 108

7641 Group

REJ09B0336-0200

APPENDIX

3.3 Notes on use

3.3.3 Notes on UART

(1) Receive

•When any one of errors occurs, the summing error flag is set to “1” and the UARTx summing error

interrupt request bit is also set to “1”. If a receive error occurs, the reception does not set the

UARTx receive buffer full interrupt request bit to “1”.

•If the receive enable bit (REN) is set to “0” (disabled) while a data is being received, the receiving

operation will stop after the data has been received.

•Setting the receive initialization bit (RIN) to “1” resets the UARTx RTS control register (UxRTS) to

“8016”. After setting the RIN bit to “1”, set this UxRTS.

(2) Transmit

•Once the transmission starts, it continues until the last bit has been transmitted even though clearing

the transmit enable bit (TEN) to “0” (disabled) or inputting “H” to the CTSx pin. After completion of

the current transmission, the transmission is disabled.

•The transmit complete flag (TCM) is changed from “1” to “0” later than 0.5 to 1.5 clocks of the shift

clock. Accordingly, take it in consideration to transmit data confirming the TCM flag after the data

is written into the transmit buffer register.

(3) Register settings

•If updating a value of UARTx baud rate generator while the data is being transmitted or received,

be sure to disable the transmission and reception before updating. If the former data remains in the

UARTx transmit buffer registers 1 and 2 at retransmission, an undefined data might be output.

•The all error flags PER, FER, OER and SER are cleared to “0” when the UARTx status register is

read, at the hardware reset or initialization by setting the Transmit Initialization Bit. These flags are

also cleared to “0” by execution of bit test instructions such as BBC and BCS.

•The transmit buffer empty flag (TBE) is set to “0” when the low-order byte of transmitted data is

written into the UARTx (x = 1, 2) transmit buffer register 1. When using 9-bit character length, set

the data into the UARTx transmit buffer register 2 (high-order byte) first before the UARTx transmit

buffer register 1 (low-order byte).

•The receive buffer full flag (RBF) is set to “0” when the contents of UARTx receive buffer register

1 is read out. When using 9-bit character length, read the data from the UARTx receive buffer

•If a character bit length is 7 bits, bit 7 of the UARTx transmit/receive buffer register 1 and bits 0 to

7 of the UARTx transmit/receive buffer register 2 are ignored at transmitting; they are invalid at

receiving.

If a character bit length is 8 bits, bits 0 to 7 of the UARTx transmit/receive buffer register 2 are

ignored at transmitting; they are invalid at receiving.

If a character bit length is 9 bits, bits 1 to 7 of the UARTx transmit/receive buffer register 2 are

ignored at transmitting; they are “0” at receiving.

•The reset cannot affect the contents of baud rate generator.

(4) UART address mode

•When the MSB of the incoming data is “0” in the UART address mode, the receive buffer full flag

(RBF) is set to “1”, but the receive buffer full interrupt request bit is not set to “1”.

•An overrun error cannot be detected after the first data has been received in UART address mode.

•The UART address mode can be used in either an 8-bit or 9-bit character length. 7-bit character

length cannot be used.

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