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7641 Datasheet(PDF) 306 Page - Renesas Technology Corp |
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7641 Datasheet(HTML) 306 Page - Renesas Technology Corp |
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306 / 385 page  Rev.2.00 Aug 28, 2006 page 27 of 108 7641 Group REJ09B0336-0200 APPENDIX 3.3 Notes on use 3.3 Notes on use 3.3.1 Notes on interrupts (1) When setting external interrupt active edge When setting the external interrupt active edge (INT0, INT1, CNTR0, CNTR1), the interrupt request bit may be set to “1”. When not requiring the interrupt occurrence synchronized with these setting, take the following sequence. •Interrupt polarity select register (address 001116) •Timer X mode register (address 002716) •Timer Y mode register (address 002816) Set the above listed registers or bits as the following sequence. Fig. 3.3.1 Sequence of setting external interrupt active edge Set the corresponding interrupt enable bit to “0” (disabled) . ↓ Set the interrupt edge select bit (active edge switch bit) to “1”. ↓ NOP (one or more instructions) ↓ Set the corresponding interrupt request bit to “0” (no interrupt request issued). ↓ Set the corresponding interrupt enable bit to “1” (enabled). |
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