7641 datasheet(309/385 Pages) RENESAS

309 / 385 page

Rev.2.00

Aug 28, 2006

page 30 of 108

7641 Group

REJ09B0336-0200

APPENDIX

3.3 Notes on use

(5) Receive error flag

•The all error flags PER, FER, OER and SER are cleared to “0” when the UARTx status register is

read, at the hardware reset or initialization by setting the Transmit Initialization Bit. Accordingly,

note that these flags are also cleared to “0” by execution of bit test instructions such as BBC and

BBS, not only LDA.

(6) CTS function

•When the CTS function is enabled, the transmitted data is not transferred to the transmit shift

following data to the transmit buffer register.

(7) RTS function

•If the start bit is detected in the term of “H” assertion of RTS, its assertion count is suspended and

the RTSx pin remains “H” output. After receiving the last stop bit, the count is resumed.

•Setting the receive initialization bit (RIN) to “1” resets the UARTx RTS control register (UxRTS) to

“8016”. After setting the RIN bit to “1”, set this UxRTS.

(8) Interrupt

•When setting the transmit initialization bit (TIN) to “1”, both the transmit buffer empty flag (TBE) and

the transmit complete flag (TCM) are set to “1”, so that the transmit interrupt request occurs

independent of its interrupt source. After setting the transmit initialization bit (TIN) to “1”, clear the

transmit interrupt request bit to “0” before setting the transmit enable bit (TEN) to “1”.

•The transmit interrupt request bit is set and the interrupt request is generated by setting the transmit

enable bit (TIN) to “1” even when selecting timing that either of the following flags is set to “1” as

timing where the transmission interrupt is generated:

(1) Transmit buffer empty flag is set to “1”

(2) Transmit complete flag is set to “1”.

Therefore, when the transmit interrupt is used, set the transmit interrupt enable bit to transmit

enabled as the following sequence:

(1) Transmit enable bit is set to “1”

(2) Transmit interrupt request bit is set to “0”

(3) Transmit interrupt enable bit is set to “1”.

7641 Datasheet(PDF) 309 Page - Renesas Technology Corp