SH7018 datasheet(362/431 Pages) RENESAS

362 / 431 page

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16.7.4

Erase-Verify Mode

In erase-verify mode, data is read after memory has been erased to check whether it has been

correctly erased.

After the elapse of the erase time, erase mode is exited (the E bit in FLMCR1 is cleared, then the

ESU bit is cleared at least 10 µs later), the watchdog timer is cleared after the elapse of 10 µs or

more, and the operating mode is switched to erase-verify mode by setting the EV bit in FLMCR1.

Before reading in erase-verify mode, a dummy write of H'FF data should be made to the addresses

to be read. The dummy write should be executed after the elapse of 6 µs or more. When the flash

memory is read in this state (verify data is read in 32-bit units), the data at the latched address is

read. Wait at least 2 µs after the dummy write before performing this read operation. If the read

data has been erased (all “1”), a dummy write is performed to the next address, and erase-verify is

performed. If the read data has not been erased, set erase mode again, and repeat the erase/erase-

verify sequence in the same way. However, ensure that the erase/erase-verify sequence is not

repeated more than 100 times. When verification is completed, exit erase-verify mode, and wait

for at least 4 µs. If erasure has been completed on all the erase blocks, clear the SWE bit in

FLMCR1. If there are any unerased blocks, set 1 bit for the flash memory area to be erased, and

repeat the erase/erase-verify sequence in the same way.

SH7018 Datasheet(PDF) 362 Page - Renesas Technology Corp