SH7018 datasheet(363/431 Pages) RENESAS

363 / 431 page

347

End of erase

Start

Set SWE bit in FLMCR1

Set ESU bit in FLMCR1

Set E bit in FLMCR1

Wait 1

µs

Wait 100

µs

n = 1

Set EBR1/EBR2

Enable WDT

Wait 10 ms

Wait 10

µs

Wait 10

µs

Wait 6

µs

Set block start address to verify address

Wait 2

µs

Wait 4

µs

Start of erase

Clear E bit in FLMCR1

Clear ESU bit in FLMCR1

Set EV bit in FLMCR1

H'FF dummy write to verify address

Read verify data

Clear EV bit in FLMCR1

Wait 4

µs

Clear EV bit in FLMCR1

Clear SWE bit in FLMCR1

Disable WDT

Erase halted

Verify data = all “1”?

Last address of block?

Erasing

of all erase blocks

completed?

Erase failure

Clear SWE bit in FLMCR1

Wait 100

µs

Wait 100

µs

≥ 100?

Yes

← n + 1

Increment

address

Notes: 1. Preprogramming (setting erase block data to all “0”) is not necessary.

2. Verify data is read in 32-bit (longword) units.

3. Set only one bit in the erase block register (EBR). Two or more bits must not be set.

4. Erasing is performed in block units. For a multiple-block erase, the individual blocks must be erased sequentially.

Figure 16.13 Erase/Erase-Verify Flowchart (Single-Block Erase)

SH7018 Datasheet(PDF) 363 Page - Renesas Technology Corp

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