SH7018 datasheet(121/431 Pages) RENESAS

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105

8.2.2

Timer Mode Register (TMDR)

The TMDR is an 8-bit read/write register that sets the operating mode for each channel. The MTU

has three TMDR registers, one for each channel. TMDR is initialized to H'C0 by a power-on reset.

Channel 0: TMDR0

Bit:

——

BFB

BFA

MD3

MD2

MD1

MD0

Initial value:

R/W:

R/W

Channels 1 and 2: TMDR1, TMDR2

Bit:

——

MD3

MD2

MD1

MD0

Initial value:

R/W:

R/W

• Bits 7 and 6—Reserved: These bits are always read as 1. The write value should always be 1.

• Bit 5—Buffer Operation B (BFB): Designates whether to use the TGRB register for normal

operation, or buffer operation in combination with the TGRD register. When using TGRD as a

buffer register, no TGRD register input capture/output compares are generated.

This bit is reserved in channels 1 and 2, which have no TGRD registers. It is always read as 0.

The write value should always be 0.

Bit 5: BFB

Description

TGRB operates normally

(Initial value)

TGRB and TGRD buffer operation

• Bit 4—Buffer Operation A (BFA): Designates whether to use the TGRA register for normal

operation, or buffer operation in combination with the TGRC register. When using TGRC as a

buffer register, no TGRC register input capture/output compares are generated.

This bit is reserved in channels 1 and 2, which have no TGRC registers. It is always read as 0.

The write value should always be 0.

Bit 4: BFA

Description

TGRA operates normally

(Initial value)

TGRA and TGRC buffer operation

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