SH7018 datasheet(118/431 Pages) RENESAS

118 / 431 page

102

• Bits 7 to 5—Counter Clear 2, 1, and 0 (CCLR2, CCLR1, CCLR0): Select the counter clear

source for the TCNT counter.

Channel 0:

Bit 7:

CCLR2

Bit 6:

CCLR1

Bit 5:

CCLR0

Description

TCNT clear disabled

(Initial value)

TCNT is cleared by TGRA compare-match or input capture

TCNT is cleared by TGRB compare-match

Synchronizing clear: TCNT is cleared in synchronization with clear of

other channel counters operating in sync*

TCNT clear disabled

TCNT is cleared by TGRC compare-match or input capture*

TCNT is cleared by TGRD compare-match*

Synchronizing clear: TCNT is cleared in synchronization with clear of

other channel counters operating in sync*

Notes: 1. Setting the SYNC bit of the TSYR to 1 sets the synchronization.

2. When TGRC or TGRD are functioning as buffer registers, TCNT is not cleared because

the buffer registers have priority and compare-match/input captures do not occur.

Channels 1 and 2:

Bit 7:

Reserved*

Bit 6:

CCLR1

Bit 5:

CCLR0

Description

TCNT clear disabled

(Initial value)

TCNT is cleared by TGRA compare-match or input capture

TCNT is cleared by TGRB compare-match or input capture

Synchronizing clear: TCNT is cleared in synchronization with

clear of other channel counters operating in sync*

Notes: 1. The bit 7 of channels 1 and 2 is reserved. This bit is always read as 0. The write value

should always be 0.

2. Setting the SYNC bit of the TSYR to 1 sets the synchronization.

• Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): CKEG1 and CKEG0 select the input

clock edges. When counting is done on both edges of the internal clock the input clock

frequency becomes 1/2 (Example: both edges of

φ/4 = rising edge of φ/2).

SH7018 Datasheet(PDF) 118 Page - Renesas Technology Corp

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