SH7018 datasheet(227/431 Pages) RENESAS

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Bit 7: TDRE

Description

TDR1 contains valid transmit data

TDRE is cleared to 0 when software reads TDRE after it has been set to 1, then

writes 0 in TDRE.

TDR1 does not contain valid transmit data

(Initial value)

TDRE is set to 1 when the chip is power-on reset or in standby mode, the TE bit

in the serial control register (SCR1) is cleared to 0, or TDR1 contents are loaded

into TSR1, so new data can be written in TDR1.

• Bit 6—Receive Data Register Full (RDRF): Indicates that RDR1 contains received data.

Bit 6: RDRF

Description

RDR1 does not contain valid received data

(Initial value)

RDRF is cleared to 0 when the chip is power-on reset or in standby mode,

software reads RDRF after it has been set to 1, then writes 0 in RDRF.

RDR1 contains valid received data

RDRF is set to 1 when serial data is received normally and transferred from

RSR1 to RDR1.

Note:

The RDR1 and RDRF are not affected by detection of receive errors or by clearing of the

RE bit to 0 in the serial control register (SCR1). They retain their previous contents. If RDRF

is still set to 1 when reception of the next data ends, an overrun error (ORER) occurs and

the received data is lost.

• Bit 5—Overrun Error (ORER): Indicates that data reception ended abnormally due to an

overrun error.

Bit 5: ORER

Description

Receiving is in progress or has ended normally

(Initial value)

Clearing the RE bit to 0 in the serial control register (SCR1) does not affect the

ORER bit, which retains its previous value.

ORER is cleared to 0 when the chip is power-on reset, in standby mode, or

software reads ORER after it has been set to 1, then writes 0 in ORER.

A receive overrun error occurred

RDR1 continues to hold the data received before the overrun error, so

subsequent receive data is lost. Serial receiving cannot continue while ORER is

set to 1.

ORER is set to 1 if reception of the next serial data ends when RDRF is set to 1.

SH7018 Datasheet(PDF) 227 Page - Renesas Technology Corp