SH7713 datasheet(395/904 Pages) RENESAS

Part #	SH7713

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	904 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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Section 12 Bus State Controller (BSC)

Rev.1.50 Aug. 30, 2006 Page 355 of 860

REJ09B0288-0150

• CS4WCR

Bit

Bit Name

Initial

Value

R/W

Description

31 to



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

BAS

R/W

Byte Access Selection for Byte-Selection SRAM

Specifies the

WEn (BEn) and RD/WR signal timing when

the byte-selection SRAM interface is used.

0: Asserts the

WEn (BEn) signal at the read/write timing

and asserts the RD/

WR signal during the write access

cycle.

1: Asserts the

WEn (BEn) signal during the read/write

access cycle and asserts the RD/

WR signal at the write

timing.



Reserved

This bit is always read as 0. The write value should always

be 0.

WW2

WW1

WW0

R/W

Number of Write Access Wait Cycles

Specify the number of cycles that are necessary for write

access.

000: The same cycles as WR3 to WR0 setting (read access

wait)

001: 0 cycle

010: 1 cycle

011: 2 cycles

100: 3 cycles

101: 4 cycles

110: 5 cycles

111: 6 cycles

15 to



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

SH7713 Datasheet(PDF) 395 Page - Renesas Technology Corp

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