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SH7713 Datasheet(PDF) 447 Page - Renesas Technology Corp |
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SH7713 Datasheet(HTML) 447 Page - Renesas Technology Corp |
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447 / 904 page  Section 12 Bus State Controller (BSC) Rev.1.50 Aug. 30, 2006 Page 407 of 860 REJ09B0288-0150 Setting A2/3 BSZ [1:0] A2/3 ROW [1:0] A2/3 COL [1:0] 11 (32 bits) 01 (12 bits) 10 (10 bits) Output Pin of This LSI Row Address Output Column Address Output Synchronous DRAM Pin Function A2 A12 A2 A0 A1 A11 A1 A0 A10 A0 Unused Example of connected memory 512-Mbit product (4 Mwords x 32 bits x 4 banks, column 10 bits product): 1 256-Mbit product (4 Mwords x 16 bits x 4 banks, column 10 bits product): 2 Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the access mode. 2. Bank address specification |
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