SH7713 datasheet(482/904 Pages) RENESAS

482 / 904 page

Section 12 Bus State Controller (BSC)

Rev.1.50 Aug. 30, 2006 Page 442 of 860

REJ09B0288-0150

CKIO

A25 to A0

D31 to D0

DACK

WAIT

TB2

Twb

TB2

Twb

TB2

Twb

RD/

Figure 12.32 Burst ROM (Clock Asynchronous) Access (Bus Width = 32 Bits,

16-byte Transfer (Number of Bursts = 4), Access Wait for First Time = 2,

Access Wait for 2nd Time and after = 1)

12.5.7

Byte-Selection SRAM Interface

The byte-selection SRAM interface is for access to an SRAM which has a byte-selection pin

(

WEn (BEn)). This interface has 16-bit data pins and accesses SRAMs having upper and lower

byte selection pins, such as UB and LB.

When the BAS bit in CSnWCR is cleared to 0 (initial value), the write access timing of the byte-

selection SRAM interface is the same as that for the normal space interface. While in read access

of a byte-selection SRAM interface, the byte-selection signal is output from the

WEn (BEn) pin,

which is different from that for the normal space interface. The basic access timing is shown in

figure 12.33. In write access, data is written to the memory according to the timing of the byte-

selection pin (

WEn (BEn)). For details, refer to the data sheet for the corresponding memory.

If the BAS bit in CSnWCR is set to 1, the

WEn (BEn) pin and RD/WR pin timings change. Figure

12.34 shows the basic access timing. In write access, data is written to the memory according to

the timing of the write enable pin (RD/

WR). The data hold timing from RD/WR negation to data

write must be acquired by setting the HW[1:0] bits in CSnWCR. Figure 12.35 shows the access

timing when a software wait is specified.

SH7713 Datasheet(PDF) 482 Page - Renesas Technology Corp