SH7713 datasheet(480/904 Pages) RENESAS

480 / 904 page

Section 12 Bus State Controller (BSC)

Rev.1.50 Aug. 30, 2006 Page 440 of 860

REJ09B0288-0150

CKIO

CKE

A25 to A0

CSn

RD/

RAS

DQMxx

D31 to D0

Tpw

DACKn*2

Tdpd

A12/A11*1

CAS

Notes: 1. Address pin to be connected to the A10 pin of SDRAM.

2. The waveform for DACKn is when active low is specified.

Trc

Hi-Z

Trc

Figure 12.31 Transition Timing in Deep Power-Down Mode

12.5.6

Burst ROM (Clock Asynchronous) Interface

The burst ROM (clock asynchronous) interface is used to access a memory with a high-speed read

function using a method of address switching called the burst mode or page mode. In a burst ROM

(clock asynchronous) interface, basically the same access as the normal space is performed, but

the 2nd and subsequent accesses are performed only by changing the address, without negating the

RD signal at the end of the 1st cycle. In the 2nd and subsequent accesses, addresses are changed at

the falling edge of the CKIO.

For the 1st access cycle, the number of wait cycles specified by the W[3:0] bits in CSnWCR is

inserted. For the 2nd and subsequent access cycles, the number of wait cycles specified by the

BW[1:0] bits in CSnWCR is inserted.

In the access to the burst ROM (clock asynchronous), the

BS signal is asserted only to the first

access cycle. An external wait input is valid only to the first access cycle.

In the single access or write access that do not perform the burst operation in the burst ROM

(clock asynchronous) interface, access timing is same as a normal space.

SH7713 Datasheet(PDF) 480 Page - Renesas Technology Corp