SH7713 datasheet(476/904 Pages) RENESAS

476 / 904 page

Section 12 Bus State Controller (BSC)

Rev.1.50 Aug. 30, 2006 Page 436 of 860

REJ09B0288-0150

Burst read/burst write (burst length 1):

Data Bus Width

CAS Latency

Access Address

External Address Pin

16 bits

′A4FD5040

′0000040

′A4FD5060

′0000060

32 bits

′A4FD5080

′0000080

′A4FD50C0

′00000C0

Mode register setting timing is shown in figure 12.29. A PALL command (all bank precharge

command) is firstly issued. A REF command (auto refresh command) is then issued 8 times. An

MRS command (mode register write command) is finally issued. Idle cycles, of which number is

specified by the TRP[1:0] bits in CSnWCR, are inserted between the PALL and the first REF. Idle

cycles, of which number is specified by the TRC[1:0]bits in CSnWCR, are inserted between REF

and REF, and between the 8th REF and MRS. Idle cycles, of which number is one or more, are

inserted between the MRS and a command to be issued next.

It is necessary to keep idle time of certain cycles for SDRAM before issuing PALL command after

power-on. Refer the manual of the SDRAM for the idle time to be needed. When the pulse width

of the reset signal is longer then the idle time, mode register setting can be started immediately

after the reset, but care should be taken when the pulse width of the reset signal is shorter than the

idle time.

SH7713 Datasheet(PDF) 476 Page - Renesas Technology Corp