SH7713 datasheet(473/904 Pages) RENESAS

473 / 904 page

Section 12 Bus State Controller (BSC)

Rev.1.50 Aug. 30, 2006 Page 433 of 860

REJ09B0288-0150

Figure 12.27 shows the access timing in low-frequency mode. In this mode, commands, addresses,

and write data are output in synchronization with the falling edge of CKIO, which is half a cycle

delayed than the normal timing. Read data is fetched at the rising edge of CKIO, which is half a

cycle faster than the normal timing. This timing allows the hold time of commands, addresses,

write data, and read data to be extended.

If SDRAM is operated at a high frequency with the SLOW bit set to 1, the setup time of

commands, addresses, write data, and read data are not guaranteed. Take the operating frequency

and timing design into consideration when making the SLOW bit setting.

CKIO

A25 to A0

CSn

RD/

D31 to D0

Tc1

DACKn*2

Td1

A12/A11*1

Tde

Tap

Tc1

Tnop

Trwl

Tap

CKE

RAS

DQMxx

CAS

Notes: 1. Address pin to be connected to the A10 pin of SDRAM.

2. The waveform for DACKn is when active low is specified.

(High)

Figure 12.27 Access Timing in Low-Frequency Mode

Power-Down Mode: If the PDOWN bit in SDCR is set to 1, the SDRAM is placed in the power-

down mode by bringing the CKE signal to the low level in the non-access cycle. This power-down

mode can effectively lower the power consumption in the non-access cycle. However, please note

SH7713 Datasheet(PDF) 473 Page - Renesas Technology Corp