SH7713 datasheet(470/904 Pages) RENESAS

Part #	SH7713

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	904 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

Logo

470 / 904 page

Section 12 Bus State Controller (BSC)

Rev.1.50 Aug. 30, 2006 Page 430 of 860

REJ09B0288-0150

CKIO

A25 to A0

CSn

RD/

D31 to D0

Tpw

DACKn*2

Trr

A12/A11*1

Trc

Hi-z

RAS

DQMxx

CAS

Notes: 1. Address pin to be connected to the A10 pin of SDRAM.

2. The waveform for DACKn is when active low is specified.

Figure 12.25 Auto-Refresh Timing

2. Self-refreshing

Self-refresh mode in which the refresh timing and refresh addresses are generated within the

synchronous DRAM. Self-refreshing is activated by setting both the RMODE bit and the

RFSH bit in SDCR to 1. After starting the self-refreshing, PALL command is issued in Tp

cycle after the completion of the pre-charging bank. A SELF command is then issued after

inserting idle cycles of which number is specified by the TRP[1:0] bits in CSnWSR.

Synchronous DRAM cannot be accessed while in the self-refresh state. Self-refresh mode is

cleared by clearing the RMODE bit to 0. After self-refresh mode has been cleared, command

issuance is disabled for the number of cycles specified by the TRC[1:0] bits in CSnWCR.

SH7713 Datasheet(PDF) 470 Page - Renesas Technology Corp