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SH7713 Datasheet(PDF) 468 Page - Renesas Technology Corp |
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SH7713 Datasheet(HTML) 468 Page - Renesas Technology Corp |
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468 / 904 page  Section 12 Bus State Controller (BSC) Rev.1.50 Aug. 30, 2006 Page 428 of 860 REJ09B0288-0150 CKIO A25 to A0 CSn RD/ WR D31 to D0 BS Tpw DACKn*2 Tp Tc1 A12/A11*1 Tr RAS DQMxx CAS Notes: 1. Address pin to be connected to the A10 pin of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 12.24 Single Write Timing (Bank Active, Different Row Addresses) Refreshing: This LSI has a function for controlling synchronous DRAM refreshing. Auto- refreshing can be performed by clearing the RMODE bit to 0 and setting the RFSH bit to 1 in SDCR. A continuous refreshing can be performed by setting the RRC[2:0] bits in RTCSR. If synchronous DRAM is not accessed for a long period, self-refresh mode, in which the power consumption for data retention is low, can be activated by setting both the RMODE bit and the RFSH bit to 1. |
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