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SH7713 Datasheet(PDF) 475 Page - Renesas Technology Corp

Part # SH7713
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  904 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7713 Datasheet(HTML) 475 Page - Renesas Technology Corp

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Section 12 Bus State Controller (BSC)
Rev.1.50 Aug. 30, 2006 Page 435 of 860
REJ09B0288-0150
wrap type = sequential, and burst length 1 supported by the LSI, arbitrary data is written in a byte-
size access to the addresses shown in table 12.19. In this time 0 is output at the external address
pins of A12 or later.
Table 12.19 Access Address in SDRAM Mode Register Write
• Setting for Area 2 (SDMR2)
Burst read/single write (burst length 1):
Data Bus Width
CAS Latency
Access Address
External Address Pin
16 bits
2
H
′A4FD4440
H
′0000440
3
H
′A4FD4460
H
′0000460
32 bits
2
H
′A4FD4880
H
′0000880
3
H
′A4FD48C0
H
′00008C0
Burst read/burst write (burst length 1):
Data Bus Width
CAS Latency
Access Address
External Address Pin
16 bits
2
H
′A4FD4040
H
′0000040
3
H
′A4FD4060
H
′0000060
32 bits
2
H
′A4FD4080
H
′0000080
3
H
′A4FD40C0
H
′00000C0
• Setting for Area 3 (SDMR3)
Burst read/single write (burst length 1):
Data Bus Width
CAS Latency
Access Address
External Address Pin
16 bits
2
H
′A4FD5440
H
′0000440
3
H
′A4FD5460
H
′0000460
32 bits
2
H
′A4FD5880
H
′0000880
3
H
′A4FD58C0
H
′00008C0



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