SH7713 datasheet(871/904 Pages) RENESAS

Part #	SH7713

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	904 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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871 / 904 page

Section 24 Electrical Characteristics

Rev.1.50 Aug. 30, 2006 Page 831 of 860

REJ09B0288-0150

24.3.9

SCIF Module Signal Timing

Table 24.11 SCIF Module Signal Timing

(Conditions: V

CCQ = VCCQ-RTC = 3.0 to 3.6 V, VCC = VCC-PLL1 = VCC-PLL2 = 1.4 to 1.6 V,

SSQ = VSS = VSSQ-RTC = VSS-PLL1 = VSS-PLL2 = 0 V, Ta = –20 to 75°C)

Module

Item

Symbol

Min.

Max.

Unit

Figure

Clock

synchronization

—

SCIF0,

SCIF1

Input clock

cycle

Asynchroniza-

tion

Scyc

—

Pcyc

24.51

24.52

Input clock rise time

SCKR

—

1.5

24.51

Input clock fall time

SCKF

—

1.5

Input clock pulse width

SCKW

0.4

0.6

Scyc

Transmission data delay time

TXD

—

3 t

Pcyc* + 50

24.52

Receive data setup time

(clock synchronization)

RXS

2 t

Pcyc*

—

Receive data hold time

(clock synchronization)

RXH

2 t

Pcyc*

—

RTS delay time

RTSD

—

100

CTS setup time

(clock synchronization)

CTSS

100

—

CTS hold time

(clock synchronization)

CTSH

100

—

Note: * t

Pcyc indicates a peripheral clock (Pφ) cycle.

tSCKW

tSCKR

tSCKF

tScyc

SCIFnCK

Figure 24.51 SCIFnCK Input Clock Timing

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