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SH7713 Datasheet(PDF) 867 Page - Renesas Technology Corp |
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SH7713 Datasheet(HTML) 867 Page - Renesas Technology Corp |
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867 / 904 page ![]() Section 24 Electrical Characteristics Rev.1.50 Aug. 30, 2006 Page 827 of 860 REJ09B0288-0150 Trc Trc Trc Trc Trr Tpw Tp Trc t CSD2 t CSD2 t CSD2 t CSD2 t AD3 t AD3 t AD3 t AD3 t RWD2 t RWD2 t RWD2 t RASD2 t RASD2 t RASD2 t RASD2 CKIO A25 to A0 CSn RD/ WR A12/A11*1 D31 to D0 RAS t CASD2 t CASD2 CAS (Hi-Z) BS CKE DQMxx DACKn*2 t CKED2 t CKED2 Notes: 1. Address pin to be connected to A10 of SDRAM. 2. DACKn is a waveform when active-low is specified. Figure 24.46 Synchronous DRAM Self-Refresh Timing (TRP = 2 Cycle, Low-Frequency Mode) |
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