SH7713 datasheet(224/904 Pages) RENESAS

224 / 904 page

Section 5 Memory Management Unit (MMU)

Rev.1.50 Aug. 30, 2006 Page 184 of 860

REJ09B0288-0150

1. P0, P3, and U0 Areas

The P0, P3, and U0 areas can be address translated by the TLB and can be accessed through

the cache. If the MMU is enabled, these areas can be mapped to any physical address space in

1- or 4-kbyte page units via the TLB. If the CE bit in the cache control register (CCR1) is set

to 1 and if the corresponding cache enable bit (C bit) of the TLB entry is set to 1, access via the

cache is enabled. If the MMU is disabled, replacing the upper three bits of an address in these

areas with 0s creates the address in the corresponding physical address space. If the CE bit of

the CCR1 register is set to 1, access via the cache is enabled. When the cache is used, either

the copy-back or write-through mode is selected for write access via the WT bit in CCR1.

If these areas are mapped to the on-chip module control register area or on-chip memory area

in area 1 in the physical address space via the TLB, the C bit of the corresponding page must

be cleared to 0.

2. P1 Area

The P1 area can be accessed via the cache and cannot be address-translated by the TLB.

Whether the MMU is enabled or not, replacing the upper three bits of an address in these areas

with 0s creates the address in the corresponding physical address space. Use of the cache is

determined by the CE bit in the cache control register (CCR1). When the cache is used, either

the copy-back or write-through mode is selected for write access by the CB bit in the CCR1

3. P2 Area

The P2 area cannot be accessed via the cache and cannot be address-translated by the TLB.

Whether the MMU is enabled or not, replacing the upper three bits of an address in this area

with 0s creates the address in the corresponding physical address space.

4. P4 Area

The P4 area is mapped to the on-chip I/O of this LSI. This area cannot be accessed via the

cache and cannot be address-translated by the TLB. Figure 5.4 shows the configuration of the

P4 area.

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