SH7713 datasheet(227/904 Pages) RENESAS

227 / 904 page

Section 5 Memory Management Unit (MMU)

Rev.1.50 Aug. 30, 2006 Page 187 of 860

REJ09B0288-0150

H'F000 0000

H'F100 0000

H'F200 0000

H'F300 0000

H'F400 0000

H'FFFF FFFF

H'FC00 0000

Reserved Area

Cache Address Array

Cache Data Array

TLB Address Array

TLB Data Array

H'E000 0000

Control Register Area

Figure 5.4 P4 Area

The area from H'F000 0000 to H'F0FF FFFF is for direct access to the cache address array. For

more information, see section 6.4, Memory-Mapped Cache.

The area from H'F100 0000 to H'F1FF FFFF is for direct access to the cache data array. For more

information, see section 6.4, Memory-Mapped Cache.

The area from H'F200 0000 to H'F2FF FFFF is for direct access to the TLB address array. For

more information, see section 5.6, Memory-Mapped TLB.

The area from H'F300 0000 to H'F3FF FFFF is for direct access to the TLB data array. For more

information, see section 5.6, Memory-Mapped TLB.

The area from H'FC00 0000 to H'FFFF FFFF is reserved for registers of the on-chip peripheral

modules. For more information, see section 23, List of Registers.

5. Uxy Area

The Uxy area is mapped to the on-chip memory of this LSI. This area is made usable in user

mode when the DSP bit in the SR register is set to 1. In user mode, accessing this area when

the DSP bit is 0 will result in an address error. This area cannot be accessed via the cache and

cannot be address-translated by the TLB. For more information on the Uxy area, see section 7,

X/Y Memory.

SH7713 Datasheet(PDF) 227 Page - Renesas Technology Corp