SH7713 datasheet(231/904 Pages) RENESAS

231 / 904 page

Section 5 Memory Management Unit (MMU)

Rev.1.50 Aug. 30, 2006 Page 191 of 860

REJ09B0288-0150

5.2.2

Page Table Entry Register Low (PTEL)

The page table entry register low (PTEL) register residing at address H'FFFFFFF4, and used to

store the physical page number and page management information to be recorded in the TLB by

the LDTLB instruction. The contents of this register are only modified in response to a software

command.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 29



All 0

R/W

Reserved

These bits are always read as 0. The write value

should always be 0.

28 to 10

PPN



Number of Physical Page



R/W



6, 5



Page management information

For more details, see section 5.3, TLB Functions

5.2.3

Translation Table Base Register (TTB)

The translation table base register (TTB) residing at address H'FFFFFFF8, which points to the

base address of the current page table. The hardware does not set any value in TTB automatically.

TTB is available to software for general purposes. The initial value is undefined.

5.2.4

MMU Control Register (MMUCR)

The MMU control register (MMUCR) residing at address H'FFFFFFE0, which makes the MMU

settings described in figure 5.3. Any program that modifies MMUCR should reside in the P1 or P2

area.

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