SH7713 datasheet(233/904 Pages) RENESAS

Part #	SH7713

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	904 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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Section 5 Memory Management Unit (MMU)

Rev.1.50 Aug. 30, 2006 Page 193 of 860

REJ09B0288-0150

Bit

Bit Name

Initial

Value

R/W

Description

R/W

Address translation

Enables/disables the MMU.

0: MMU disabled

1: MMU enabled

5.3

TLB Functions

5.3.1

Configuration of the TLB

The TLB caches address translation table information located in the external memory. The address

translation table stores the logical page number and the corresponding physical number, the

address space identifier, and the control information for the page, which is the unit of address

translation. Figure 5.6 shows the overall TLB configuration. The TLB is 4-way set associative

with 128 entries. There are 32 entries for each way. Figure 5.7 shows the configuration of virtual

addresses and TLB entries.

Entry 1

Address Array

Data Array

Entry 0

Entry 1

Entry 31

Way 0 to 3

VPN(11-10)

VPN(31-17)

ASID(7-0)

Entry 0

Entry 31

PPN(28-10) PR(1-0) SZ C D SH

Figure 5.6 Overall Configuration of the TLB

SH7713 Datasheet(PDF) 233 Page - Renesas Technology Corp