SH7713 datasheet(247/904 Pages) RENESAS

247 / 904 page

Section 5 Memory Management Unit (MMU)

Rev.1.50 Aug. 30, 2006 Page 207 of 860

REJ09B0288-0150

5.5.3

TLB Invalid Exception

A TLB invalid exception results when the virtual address is compared to a selected TLB entry

address array and a match is found but the entry is not valid (the V bit is 0). TLB invalid exception

processing includes both hardware and software operations.

Hardware Operations: In a TLB invalid exception, this hardware executes a set of prescribed

operations, as follows:

1. The VPN number of the virtual address causing the exception is written to the PTEH register.

2. The virtual address causing the exception is written to the TEA register.

3. Either exception code H'040 for a load access, or H'060 for a store access, is written to the

EXPEVT register.

4. The PC value indicating the address of the instruction in which the exception occurred is

written to the SPC. If the exception occurred in a delay slot, the PC value indicating the

address of the delayed branch instruction is written to the SPC.

5. The contents of SR at the time of the exception are written into SSR.

6. The mode (MD) bit in SR is set to 1 to place the privileged mode.

7. The block (BL) bit in SR is set to 1 to mask any further exception requests.

8. The RB bit in SR is set to 1.

9. The way number causing the exception is written to RC in MMUCR.

10. Execution branches to the address obtained by adding the value of the VBR contents and

H'00000100, and the TLB protection violation exception handler starts.

Software (TLB Invalid Exception Handler) Operations: The software searches the page tables

in external memory and assigns the required page table entry. Upon retrieving the required page

table entry, software must execute the following operations:

1. Write the values of the physical page number (PPN) field and the values of the protection key

(PR), page size (SZ), cacheable (C), dirty (D), share status (SH), and valid (V) bits of the page

table entry recorded in the external memory to the PTEL register.

2. If using software for way selection for entry replacement, write the desired value to the RC

field in MMUCR.

3. Issue the LDTLB instruction to load the contents of PTEH and PTEL into the TLB.

4. Issue the RTE instruction to terminate the handler and return to the instruction stream. The

RTE instruction should be issued after two LDTLB instructions.

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