SH7713 datasheet(246/904 Pages) RENESAS

246 / 904 page

Section 5 Memory Management Unit (MMU)

Rev.1.50 Aug. 30, 2006 Page 206 of 860

REJ09B0288-0150

1. Write the value of the physical page number (PPN) field and the protection key (PR), page size

(SZ), cacheable (C), dirty (D), share status (SH), and valid (V) bits of the page table entry

recorded in the address translation table in the external memory into the PTEL register.

2. If using software for way selection for entry replacement, write the desired value to the RC

field in MMUCR.

3. Issue the LDTLB instruction to load the contents of PTEH and PTEL into the TLB.

4. Issue the return from exception handler (RTE) instruction to terminate the handler routine and

return to the instruction stream.

5.5.2

TLB Protection Violation Exception

A TLB protection violation exception results when the virtual address and the address array of the

selected TLB entry are compared and a valid entry is found to match, but the type of access is not

permitted by the access rights specified in the PR field. TLB protection violation exception

processing includes both hardware and software operations.

Hardware Operations: In a TLB protection violation exception, this hardware executes a set of

prescribed operations, as follows:

1. The VPN field of the virtual address causing the exception is written to the PTEH register.

2. The virtual address causing the exception is written to the TEA register.

3. Either exception code H'0A0 for a load access, or H'0C0 for a store access, is written to the

EXPEVT register.

4. The PC value indicating the address of the instruction in which the exception occurred is

written into SPC (if the exception occurred in a delay slot, the PC value indicating the address

of the related delayed branch instruction is written into SPC).

5. The contents of SR at the time of the exception are written to SSR.

6. The MD bit in SR is set to 1 to place the privileged mode.

7. The BL bit in SR is set to 1 to mask any further exception requests.

8. The RB bit in SR is set to 1.

9. The way that generated the exception is set in the RC field in MMUCR.

10. Execution branches to the address obtained by adding the value of the VBR contents and

H'00000100 to invoke the TLB protection violation exception handler.

Software (TLB Protection Violation Handler) Operations: Software resolves the TLB

protection violation and issues the RTE (return from exception handler) instruction to terminate

the handler and return to the instruction stream. Issue the RTE instruction after issuing two

instructions from the LDTLB instruction.

SH7713 Datasheet(PDF) 246 Page - Renesas Technology Corp