SH7713 datasheet(242/904 Pages) RENESAS

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Section 5 Memory Management Unit (MMU)

Rev.1.50 Aug. 30, 2006 Page 202 of 860

REJ09B0288-0150

VPN(31-17)

VPN(11-10)

ASID(7-0)

VPN

ASID

VPN

0SV 0 0 RC 0 TF IX AT

PPN

0 V 0 PR SZ C D SH 0

Write

PPN(28-10) PR(1-0) SZ

D SH

Write

Data Array

Address Array

Way Selection

Way 0 to 3

MMUCR

Index

PTEH Register

31 29 28

PTEL Register

0 0

Figure 5.11 Operation of LDTLB Instruction

5.4.4

Avoiding Synonym Problems

When a 1- or 4-kbyte page is recorded in a TLB entry, a synonym problem may arise. If a number

of virtual addresses are mapped onto a single physical address, the same physical address data will

be recorded in a number of cache entries, and it will not be possible to guarantee data congruity.

The reason that this problem occurs is explained below with reference to figure 5.12. The

relationship between bit n of the virtual address and cache size is shown in the following table.

Cache Size

Bit n of Virtual Address

16 kbytes

32 kbytes

To achieve high-speed operation of this LSI’s cache, an index number is created using virtual

address [n:4]. When a 1-kbyte page is used, virtual address [n:10] is subject to address translation

and when a 4-kbyte page is used, a virtual address [n:12] is subject to address translation.

Therefore, the physical address [n:10] may not be the same as the virtual address [n:10].

For example, assume that, with 1-kbyte page TLB entries, TLB entries for which the following

translation has been performed are recorded in two TLBs:

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