SH7713 datasheet(240/904 Pages) RENESAS

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Section 5 Memory Management Unit (MMU)

Rev.1.50 Aug. 30, 2006 Page 200 of 860

REJ09B0288-0150

5.4

MMU Functions

5.4.1

MMU Hardware Management

There are two kinds of MMU hardware management as follows.

1. The MMU decodes the virtual address accessed by a process and performs address translation

by controlling the TLB in accordance with the MMUCR settings.

2. In address translation, the MMU receives page management information from the TLB, and

determines the MMU exception and whether the cache is to be accessed (using the C bit). For

details of the determination method and the hardware processing, see section 5.5, MMU

Exceptions.

5.4.2

MMU Software Management

There are three kinds of MMU software management, as follows.

1. MMU register setting

MMUCR setting, in particular, should be performed in areas P1 and P2 for which address

translation is not performed. Also, since SV and IX bit changes constitute address translation

system changes, in this case, TLB flushing should be performed by simultaneously writing 1 to

the TF bit also. Since MMU exceptions are not generated in the MMU disabled state with the

AT bit cleared to 0, use in the disabled state must be avoided with software that does not use

the MMU.

2. TLB entry recording, deletion, and reading

TLB entry recording can be done in two ways by using the LDTLB instruction, or by writing

directly to the memory-mapped TLB. For TLB entry deletion and reading, the memory

allocation TLB can be accessed. See section 5.4.3, MMU Instruction (LDTLB), for details of

the LDTLB instruction, and section 5.6, Memory-Mapped TLB, for details of the memory-

mapped TLB.

3. MMU exception processing

When an MMU exception is generated, it is handled on the basis of information set from the

hardware side. See section 5.5, MMU Exceptions, for details.

When single virtual memory mode is used, it is possible to create a state in which physical

memory access is enabled in the privileged mode only by clearing the share status bit (SH) to 0 to

specify recording of all TLB entries. This strengthens inter-process memory protection, and

enables special access levels to be created in the privileged mode only.

SH7713 Datasheet(PDF) 240 Page - Renesas Technology Corp