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SH7713 Datasheet(PDF) 239 Page - Renesas Technology Corp |
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SH7713 Datasheet(HTML) 239 Page - Renesas Technology Corp |
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239 / 904 page  Section 5 Memory Management Unit (MMU) Rev.1.50 Aug. 30, 2006 Page 199 of 860 REJ09B0288-0150 Table 5.1 Access States Designated by D, C, and PR Bits Privileged Mode User Mode Reading Writing Reading Writing D bit 0 Permitted Initial page write exception Permitted Initial page write exception 1 Permitted Permitted Permitted Permitted C bit 0 Permitted (no caching) Permitted (no caching) Permitted (no caching) Permitted (no caching) 1 Permitted (with caching) Permitted (with caching) Permitted (with caching) Permitted (with caching) PR bit 00 Permitted TLB protection violation exception TLB protection violation exception TLB protection violation exception 01 Permitted Permitted TLB protection violation exception TLB protection violation exception 10 Permitted TLB protection violation exception Permitted TLB protection violation exception 11 Permitted Permitted Permitted Permitted |
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