SH7713 datasheet(238/904 Pages) RENESAS

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Section 5 Memory Management Unit (MMU)

Rev.1.50 Aug. 30, 2006 Page 198 of 860

REJ09B0288-0150

5.3.4

Page Management Information

In addition to the SH and SZ bits, the page management information of TLB entries also includes

D, C, and PR bits.

The D bit of a TLB entry indicates whether the page is dirty (i.e., has been written to). If the D bit

is 0, an attempt to write to the page results in an initial page write exception. For physical page

swapping between secondary memory and main memory, for example, pages are controlled so that

a dirty page is paged out of main memory only after that page is written back to secondary

memory. To record that there has been a write to a given page in the address translation table in

memory, an initial page write exception is used.

The C bit in the entry indicates whether the referenced page resides in a cacheable or non-

cacheable area of memory. When the control registers and on-chip memory in area 1 are mapped,

set the C bit to 0. The PR field specifies the access rights for the page in privileged and user modes

and is used to protect memory. Attempts at non-permitted accesses result in TLB protection

violation exceptions.

Access states designated by the D, C, and PR bits are shown in table 5.1.

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