SH7713 datasheet(241/904 Pages) RENESAS

241 / 904 page

Section 5 Memory Management Unit (MMU)

Rev.1.50 Aug. 30, 2006 Page 201 of 860

REJ09B0288-0150

Recording a 1- or 4- kbyte page TLB entry may result in a synonym problem. See section 5.4.4,

Avoiding Synonym Problems.

5.4.3

MMU Instruction (LDTLB)

The load TLB instruction (LDTLB) is used to record TLB entries. When the IX bit in MMUCR is

0, the LDTLB instruction changes the TLB entry in the way specified by the RC bit in MMUCR

to the value specified by PTEH and PTEL, using VPN bits 16 to 12 specified in PTEH as the

index number. When the IX bit in MMUCR is 1, the EX-OR of VPN bits 16 to 12 specified in

PTEH and ASID bits 4 to 0 in PTEH are used as the index number.

Figure 5.11 shows the case where the IX bit in MMUCR is 0.

When an MMU exception occurs, the virtual page number of the virtual address that caused the

exception is set in PTEH by hardware. The way is set in the RC bit of MMUCR for each

exception according to the rules (see section 5.2.4, MMU Control Register (MMUCR)).

Consequently, if the LDTLB instruction is issued after setting only PTEL in the MMU exception

processing routine, TLB entry recording is possible. Any TLB entry can be updated by software

rewriting of PTEH and the RC bits in MMUCR.

As the LDTLB instruction changes address translation information, there is a risk of destroying

address translation information if this instruction is issued in the P0, U0, or P3 area. Make sure,

therefore, that this instruction is issued in the P1 or P2 area. Also, an instruction associated with an

access to the P0, U0, or P3 area (such as the RTE instruction) should be issued at least two

instructions after the LDTLB instruction.

SH7713 Datasheet(PDF) 241 Page - Renesas Technology Corp