SH7713 datasheet(253/904 Pages) RENESAS

253 / 904 page

Section 5 Memory Management Unit (MMU)

Rev.1.50 Aug. 30, 2006 Page 213 of 860

REJ09B0288-0150

5.6.3

Usage Examples

Invalidating Specific Entries: Specific TLB entries can be invalidated by writing 0 to the entry’s

V bit. R0 specifies the write data and R1 specifies the address.

; R0=H'1547 381C

R1=H'F201 3000

; MMUCR.IX=0

; the V bit of way 0 of the entry selected by the VPN(16–12)=B'1 0011

; index is cleared to0,achieving invalidation.

MOV.L

R0,@R1

Reading the Data of a Specific Entry: This example reads the data section of a specific TLB

entry. The bit order indicated in the data field in figure 5.14 (2) is read. R0 specifies the address

and the data section of a selected entry is read to R1.

; R0

=H'F300 4300

VPN(16-12)=B'00100

Way 3

; MOV.L @R0,R1

5.7

Usage Note

The following operations should be performed in the P1 or P2 areas. In addition, when the P0, P3,

or U0 areas are accessed consecutively (this access includes instruction fetching), the instruction

code should be placed at least two instructions after the instruction that executes the following

operations.

1. Modification of SR.MD or SR.BL

2. Execution of the LDTLB instruction

3. Write to the memory-mapped TLB

4. Modification of MMUCR

5. Modification of PTEH.ASID

SH7713 Datasheet(PDF) 253 Page - Renesas Technology Corp