SH7713 datasheet(257/904 Pages) RENESAS

257 / 904 page

Section 6 Cache

Rev.1.50 Aug. 30, 2006 Page 217 of 860

REJ09B0288-0150

6.2

The cache has the following registers. For details on register addresses and register states during

each process, refer to section 23, List of Registers.

• Cache control register 1 (CCR1)

• Cache control register 2 (CCR2)

• Cache control register 3 (CCR3)

6.2.1

Cache Control Register 1 (CCR1)

The cache is enabled or disabled using the CE bit in CCR1. CCR1 also has a CF bit (which

invalidates all cache entries), and WT and CB bits (which select either write-through mode or

write-back mode). Programs that change the contents of the CCR1 register should be placed in

address space that is not cached.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 4

—

All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

R/W

Cache Flush

Writing 1 flushes all cache entries (clears the V, U,

and LRU bits of all cache entries to 0). This bit is

always read as 0. Write-back to external memory is

not performed when the cache is flushed.

R/W

Write-Back

Indicates the cache’s operating mode for space P1.

0: Write-through mode

1: Write-back mode

R/W

Write-Through

Indicates the cache’s operating mode for spaces P0,

U0, and P3.

0: Write-back mode

1: Write-through mode

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