SH7713 datasheet(259/904 Pages) RENESAS

259 / 904 page

Section 6 Cache

Rev.1.50 Aug. 30, 2006 Page 219 of 860

REJ09B0288-0150

Bit

Bit Name

Initial

Value

R/W

Description

31 to 17

—

All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

R/W

Lock enable (LE)

Controls cache lock mode.

0: Enters cache lock mode when the DSP bit of the

SR register is set to 1.

1: Enters cache lock mode regardless of the DSP bit

value.

15 to 10

—

All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

W3LOAD

W3LOCK

R/W

Way 3 Load (W3LOAD)

Way 3 Lock (W3LOCK)

When the cache is missed by a prefetch instruction

while in cache lock mode and when bits W3LOAD

and W3LOCK in CCR2 are set to 1, the data is

always loaded into way 3. Under any other

condition, the prefetched data is loaded into the way

to which LRU points.

7 to 2

—

All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

W2LOAD

W2LOCK

R/W

Way 2 Load (W2LOAD)

Way 2 Lock (W2LOCK)

When the cache is missed by a prefetch instruction

while in cache lock mode and when bits W2LOAD

and W2LOCK in CCR2 are set to 1, the data is

always loaded into way 2. Under any other

condition, the prefetched data is loaded into the way

to which LRU points.

Note:

W2LOAD and W3LOAD should not be set to 1 at the same time.

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