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SH7713 Datasheet(PDF) 265 Page - Renesas Technology Corp |
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SH7713 Datasheet(HTML) 265 Page - Renesas Technology Corp |
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265 / 904 page ![]() Section 6 Cache Rev.1.50 Aug. 30, 2006 Page 225 of 860 REJ09B0288-0150 Longword 0 Longword 1 Longword 2 Longword 3 PA (31 to 4) PA (31 to 4): Longword 0 to 3: Physical address written to external memory One line of cache data to be written to external memory Figure 6.3 Write-Back Buffer Configuration 6.3.6 Coherency of Cache and External Memory Use software to ensure coherency between the cache and the external memory. When memory shared by this LSI and another device is placed in an address space to which caching applies, use the memory-mapped cache to make the data invalid and written back, as required. Memory that is shared by this LSI’s CPU and DMAC should also be handled in this way. |
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