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SH7713 Datasheet(PDF) 269 Page - Renesas Technology Corp |
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SH7713 Datasheet(HTML) 269 Page - Renesas Technology Corp |
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269 / 904 page ![]() Section 6 Cache Rev.1.50 Aug. 30, 2006 Page 229 of 860 REJ09B0288-0150 (1) Address array access (a) Address specification Read access Write access (b) Data specification (both read and write accesses) (2) Data array access (both read and write accesses) (a) Address specification 31 24 23 15 14 13 12 4 3 0 1111 0000 *--------* W Entry address 31 24 23 15 14 13 12 4 3 0 1111 0000 *--------* W Entry address 2 A 31 10 4 3 0 LRU 2 XX 9 Tag address (28 to 10) U V 1 31 24 23 15 14 13 12 4 3 0 1111 0001 *--------* W Entry address 1 2 L (b) Data specification 31 0 Longword *: Don’t care bit X: 0 for read, don’t care for write 0 * 0 0 * 0 0 2 0 0 30 29 28 0 0 0 Figure 6.5 Specifying Address and Data for Memory-Mapped Cache Access (32 kbytes mode) |
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